ICTACT Journal on Microelectronics

R. Vinoth ¹, P. Jennifer ¹, S. Ramasamy ¹

Affiliations
1 Department of Electronics and Communication Engineering, R.M.K. Engineering College, IN

Abstract

Flip-flops are the basic building blocks of any sequential circuits which occupy the maximum area in a circuit. So the robustness of the system greatly depends on the reliable operation of the flip-flop. In this work the PowerPC 603 flip-flop is simulated and analyzed to measure its reliability against variations in supply voltage and temperature. Performance analysis has been made by having Power, Delay and PDP as Figures of Merit. The acquired simulation results revealed the different sources of power consumption in different scenarios. The simulated results using finer technologies with Synopsys HSPICE prove that PowerPC 603 is a resilient flip-flop for all corners.

Keywords

PowerPC 603, Flip-Flop, Low Power.

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R. Vinoth ¹, S. Ramasamy ²

Affiliations
1 Automotive Infotainment Systems, Microchip Technology Pvt. Ltd., IN
2 School of Electrical Engineering and Computing, Addis Ababa Science and Technology University, ET

Abstract

Design of an analog circuit depends on several factors such as design methodology, good modeling and technology characterization. This work focuses on designing a high speed (1.6GHz) latched comparator with low power consumption suitable for ADCs in SoC applications. The latched comparator is designed with StrongArm latch as the primary decision and amplification stage followed by a latching element to drive the output load. The StrongArm latch is a proven circuit topology suitable for all seasons. The zero static power consumption of StrongArm latch is exploited to design a low power comparator. The output latch is used to hold the previous output value during the tracking time of the comparator. The designed comparator achieves zero setup time at a clock frequency of 1.6GHz and produces digital output with a maximum delay of 180ps.The comparator is implemented with SAED 32nm technology libraries. The performance has been analyzed using HSPICE simulator.

Keywords

Latched Comparator, Strong Arm Latch, High Speed, Low Power.

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S. Ramasamy ¹, B. Venkataramani ²

Affiliations
1 Department of Electrical and Computer Engineering, Addis Ababa Science and Technology University, IN
2 Department of Electrical and Communication Engineering, National Institute of Technology, Tiruchirappalli, IN

Abstract

In this paper, an inverter based transconductor using double CMOS pair is proposed for implementation of a programmable bandpass filter suitable for Digital Radio Mondiale (DRM). Major contributions of this paper are: proposal for operating the transconductance (Gm) stage in sub-threshold region in order to minimize the power dissipation, proposal for switching in different Gm cells with suitable dummy stages for varying the centre frequency (F-tuning) and filter pass band (Q-tuning), proposal for a digital tuning technique for the filter based on phase comparison method for PVT compensation. The filter circuit is based on a biquad Gm-C topology, which is designed and implemented on CMOS 0.18μm technology with 1.8V supply using gm/Id design methodology. The post layout simulation results demonstrate the tunability of the centre frequency from 2MHz to 11MHz with quality factor tunable up to 50, which meets the requirements of DRM (upto 30MHz). Post layout simulation results show that the filter exhibits an in-band dynamic range of 53dB at gain of 7dB. An input IP3 of up to 28dBVp is achieved for an input signal of 100mVp. The SFDR over the entire bandwidth is 57dB. These features are obtained for a total power consumption of less than 300 μW from a single 1.8 V power supply with an estimated silicon area of 0.3mm². The proposed approach guarantees the upper bound on THD to be -40dB for 300mV_pp signal swing. The use of inverters with double CMOS pair results in 34dB higher PSRR compared to those using push pull inverter.

Keywords

Continuous Time Filter, Sub-Threshold, Intermediate Frequency (IF) Bandpass Filter, Double CMOS Pair.

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